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1 1a ultra low dropout linear regulator with programmable current limiting isl80121-5 the isl80121-5 is a low dropout voltage, single output ldo with programmable current limiting. the isl80121-5 operates from input voltages of 5v to 6v with a nominal output voltage of 5v. other custom voltage options are available upon request. a sub-micron bicmos process is ut ilized for this product family to deliver the best in class analog performance and overall value. the programmable current limiting improves system reliability of end applications. an external capacitor on the soft-start pin provides an adjustable soft-sta rting ramp. the enable feature allows the part to be placed into a low quiescent current shutdown mode. this bicmos ldo will consume significantly lower quiescent current as a function of load compared to bipolar ldos, which translates into higher efficien cy and packages with smaller footprints. quiescent current is modestly compromised to achieve a very fast load transient response. features ?1.8% v out accuracy guaranteed over line, load and t j = -40c to +125c ? very low 130mv dropout voltage at v in = 5.0v ? high accuracy current limit programmable up to 1.75a ? very fast transient response ? 210v rms output noise ? power-good output ?programmable soft-start ? over-temperature protection ?small 10 ld dfn package applications ?usb devices ? telecommunications and networking ?medical equipment ? instrumentation systems ?routers and switchers ?gaming table 1. key differences between family of parts part number programmable i limit i limit (default) adj or fixed v out isl80101-adj no 1.75a adj isl80101 no 1.75a 1.8v, 2.5v, 3.3v, 5.0v isl80101a yes 1.62a adj isl80121-5 yes 0.75a 5.0v typical applications isl80121-5 v in 10 v in 9 enable 7 ss 6 gnd c in 10f c ss 5 pg 4 v out 1 v out 2 c out 10f r pg 100k ? sense 3 i set 8 i limit 0.75a = (default) 5.4v 10% v in off on v out 5.0v 1.8% isl80121-5 v in 10 v in 9 enable 7 ss 6 gnd 5.4v 10% c in 10f v in off on c ss 5 pg 4 v out 1 2 v out 5.0v 1.8% c out 10f r pg 100k ? 3 i set 8 r set 10k ? i limit 0.75 2.9 r set k () ------------------------------------- + = r sense 10 ? v out sense june 22, 2012 fn7713.5 caution: these devices are sensitive to electrostatic discharge; follow proper ic handling procedures. 1-888-intersil or 1-888-468-3774 | copyright intersil americas inc. 2010-2012. all rights reserved intersil (and design) is a trademark owned by intersil corporation or one of its subsidiaries. all other trademarks mentioned are the property of their respective owners
isl80121-5 2 fn7713.5 june 22, 2012 block diagram thermal shutdown current limiter voltage reference power good ss enable gnd pgood sense in v v out i set ordering information part number (notes 1, 2, 3) part marking v out voltage temp. range (c) package (pb-free) pkg dwg. # isl80121ir50z dzad 5.0v -40 to +125 10 ld 3x3 dfn l10.3x3 ISL80121-5EVAL2Z evaluation board notes: 1. add ?-t*? suffix for tape and reel. please refer to tb347 for details on reel specifications. 2. these intersil pb-free plastic packaged products employ spec ial pb-free material sets, molding compounds/die attach materials , and 100% matte tin plate plus anneal (e3 termination finish , which is rohs compliant and compatible wi th both snpb and pb-free soldering opera tions). intersil pb-free products are msl classified at pb-fr ee peak reflow temperatures that meet or exceed the pb-free requirements of ipc/jed ec j std-020. 3. for moisture sensitivity level (msl), please see device information page for isl80121-5 . for more information on msl, please see technical brief tb363 .
isl80121-5 3 fn7713.5 june 22, 2012 pin configuration isl80121-5 (10 ld 3x3 dfn) top view 2 3 4 1 5 9 8 7 10 6 v out v out v in v in i set enable ss pad sense pg gnd pin descriptions pin number pin name description 1, 2 v out output voltage. a minimum 10f x5r/x7r output capacito r is required for stability. see ?external capacitor requirements? on page 8 in the ?functional description? for more details. 3 sense remote voltage sense for internally fixed v out options. parasitic resistance between the v out pin and the load causes small voltage drops which degrade v out accuracy. for applications that require a stiff v out , connect the sense pin to the load. 4pgv out in regulation signal. logic low indicates v out is not in regulation, and mu st be grounded if not used. 5gndground. 6 ss external capacitor adjusts in-rush current. 7enable v in -independent chip enable. ttl and cmos compatible. 8i set current limit setting. current limit is 0. 75a when this pin is left floating. this default value can be increased by tying r set to gnd, or decreased by tying r set to v in . see ?programmable current limit? on page 7 in the ?functional description? for more details. do not short this pin to ground. 9, 10 v in input supply. a minimum of 10f x5r/x7r input capacitor is required for stability. see ?external capacitor requirements? on page 8 in ?functional description? for more details. - epad epad at ground potential. soldering it directly to gn d plane is required for thermal considerations. see ?power dissipation and thermals? on page 9 for more details.
isl80121-5 4 fn7713.5 june 22, 2012 absolute maximum ratings (note 6) thermal information v in relative to gnd . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3v to +6.5v v out relative to gnd . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3v to +6.5v pg, enable, sense, ss, i set relative to gnd . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3v to +6.5v esd rating human body model (tested per jesd22-a114) . . . . . . . . . . . . . . . .2.5kv machine model (tested per jesd22-a115). . . . . . . . . . . . . . . . . . . 250v latch up (tested per jesd78). . . . . . . . . . . . . . . . . . . . . . .100ma @ 85c thermal resistance (typical) ja (c/w) jc (c/w) 10 ld 3x3 dfn package (notes 4, 5). . . . . 48 7 maximum junction temperature (plastic package) . . . . . . . . . . . .+150c storage temperature range. . . . . . . . . . . . . . . . . . . . . . . .-65c to +150c pb-free reflow profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . see link below http://www.intersil.com/ pbfree/pb-freereflow.asp recommended operating conditions (note 7) junction temperature range (t j ) . . . . . . . . . . . . . . . . . . . . . . .-40c to +125c v in relative to gnd . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5v to 6v i set in normal operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500mv sense in normal operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . v out pg sink current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10ma caution: do not operate at or near the maximum ratings listed for extended periods of time. exposure to such conditions may adv ersely impact product reliability and result in failures not covered by warranty. notes: 4. ja is measured in free air with the componen t mounted on a high effective thermal conduc tivity test board with ?direct attach? fe atures. see tech brief tb379 . 5. for jc , the ?case temp? location is the center of the exposed metal pad on the package underside. 6. absolute maximum voltage rating is defined as the voltage applied for a lifetime average duty cycle above 6v of 1%. 7. electromigration specification defined as lifetime average junction temperature of +110c where max rated dc current = lifeti me average current. electrical specifications unless otherwise noted, all parameters are establ ished over the followin g specified conditions: v in =v out + 0.4v, v out = 5.0v, c in = c out = 10f, t j = +25c, i load = 0a. applications must follow thermal guidelines of the package to determine worst case junction temperature. please refer to ?functional description? on page 7 and tech brief tb379 . boldface limits apply over the operating temperature range, -40c to +125c. pulse load techniques used by ate to ensure t j = t a defines established limits. parameter symbol test conditions min (note 8) typ max (note 8) units dc characteristics dc output voltage accuracy v out v out + 0.4v < v in < 6v; 0a < i load < 1a -1.8 1.8 % dc input line regulation v out / v in v out + 0.4v < v in < 6.0v, v out = 5.0v 1 % dc output load regulation v out 0a < i load < 1a -1 % ground pin current i q i load = 0a, 2.2v < v in < 6v 3 5 ma i load = 1a, 2.2v < v in < 6v 5 7 ma ground pin current in shutdown i shdn enable = 0.2v, v in = 6v 0.2 12 a dropout voltage (note 9) v do i load = 1a, v in = 5.0v, v sense = 0v 90 130 mv output current limit i limit v out = 4.75v, v out + 0.4v < v in < 6v, i set is floating 0.66 0.75 0.84 a v out = 4.75v, v out + 0.4v < v in < 6v, r set = 19.33k 0.9 a thermal shutdown temperature tsd v out + 0.4v < v in < 6v 160 c thermal shutdown hysteresis (rising threshold) tsdn v out + 0.4v < v in < 6v 30 c ac characteristics input supply ripple rejection psrr f = 1khz, i load = 1a 40 db f = 1khz, i load = 100ma 40 db
isl80121-5 5 fn7713.5 june 22, 2012 output noise voltage i load = 10ma, bw = 10hz < f < 100khz 210 v rms enable pin characteristics turn-on threshold v en(high) 2.2v < v in < 6v 0.3 0.8 1.0 v hysteresis (rising threshold) v en(hys) 2.2v < v in < 6v 10 80 200 mv enable pin turn-on delay t en c out = 10f, i load = 1a 100 s enable pin leakage current v in = 6v, enable = 3v 1 a soft-start characteristics reset pull-down current i pd enable = 0v, ss = 1v 0.5 1 1.3 ma soft-start charge current i chg -3.3 -2 -0.8 a pg pin characteristics v out pg flag threshold 75 84 92 %v out v out pg flag hysteresis 4% pg flag low voltage i sink = 500a 47 100 mv pg flag leakage current v in = 6v, pg = 6v 0.05 1 a notes: 8. compliance to data sheet limits is assured by one or more methods: production test, characterization and/or design. 9. dropout is defined by the difference in supply v in and v out when the output is below its nominal regulation. electrical specifications unless otherwise noted, all parameters are establ ished over the followin g specified conditions: v in =v out + 0.4v, v out = 5.0v, c in = c out = 10f, t j = +25c, i load = 0a. applications must follow thermal guidelines of the package to determine worst case junction temperature. please refer to ?functional description? on page 7 and tech brief tb379 . boldface limits apply over the operating temperature range, -40c to +125c. pulse load techniques used by ate to ensure t j = t a defines established limits. (continued) parameter symbol test conditions min (note 8) typ max (note 8) units
isl80121-5 6 fn7713.5 june 22, 2012 typical operating performance unless otherwise noted: v in = 5.4v, v out = 5.0v, c in = c out = 10f, t j = +25c, i l = 0a. figure 1. dropout voltage vs load figure 2. output voltage vs temperature figure 3. output voltage vs output curren tfigure 4.ground curr ent vs load current figure 5. shutdown current vs te mperature figure 6. enable start-up 0 30 60 90 120 150 0 0.2 0.4 0.6 0.8 1.0 load current (a) -40c +25c +125c dropout (mv) -1.8 -1.2 -0.6 0 0.6 1.2 1.8 -50-25 0 255075100125150 junction temperature (c) dv out (%) -1.8 -1.2 -0.6 0 0.6 1.2 1.8 0 0.25 0.50 0.75 1.00 output current (a) dv out (%) +125c +25c -40c 2.85 2.90 2.95 3.00 3.05 3.10 3.15 3.20 3.25 3.30 00.20.40.60.81 ground current (ma) load current (a) -40c +25c +125c 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 -40 -25 -10 5 20 35 50 65 80 95 110 125 temperature (c) ground current (a) v in = 6v v out (5v/div) pg (5v/div) ss (2v/div) enable (2v/div) time (2ms/div)
isl80121-5 7 fn7713.5 june 22, 2012 functional description input voltage requirements the isl80121-5 is optimized for 5v output, and can operate from input voltages of 5v to 6v. due to the nature of an ldo, v in must be some margin higher than v out plus dropout at the maximum rated current of the application if active filtering (psrr) is expected from v in to v out . the generous dropout specification of this family of ldos allows applications to design for a level of efficiency that can accommodate profiles smaller than the to220/263. programmable current limit the isl80121-5 protects against overcurrent due to short-circuit and overload conditions applie d to the output. when this happens, the ldo performs as a constant current source. if the short-circuit or overload condition is removed, the output returns to normal voltage regulation operation. the current limit is set at 0.75a by default when the i set pin is left floating. this limit can be increased by tying a resistor r set from the i set pin to ground. the current limit is determined by r set as shown in equation 1: figure 11 shows the relationship between r set and the current limit when the r set is tied from i set pin to gnd. do not short this pin to ground. increasing the current limit past 1.75a may cause damage to the part and is highly discouraged. figure 7. current limit vs temperat ure figure 8. load transient response figure 9. psrr vs load figure 10. psrr vs c out typical operating performance unless otherwise noted: v in = 5.4v, v out = 5.0v, c in = c out = 10f, t j = +25c, i l = 0a. (continued) 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 -40 10 60 110 current limit (a) temperature (c) r set = 20k ? r set = open v out (50mv/div) i out = 500ma i out = 10ma time (50s/div) 0 10 20 30 40 10 100 1k 10k 100k 1m frequency (hz) magnitude (db) 100ma load 1a load 0 10 20 30 40 50 60 frequency (hz) load = 100ma magnitude (db) 10 100 1k 10k 100k 1m c out = 100f c out = 47f c out = 22f c out = 10f i limit 0.75 2.9 r set k () -------------------------- + = (eq. 1)
isl80121-5 8 fn7713.5 june 22, 2012 the current limit can be decreased from the 0.75a default by tying r set from the i set pin to v in . the current limit is then determined by both r set and v in following equation 2: figure 12 shows the relationship between r set and the current limit when r set is tied from the i set pin to v in for v in =5.4v. enable operation the enable turn-on threshold is typically 800mv with 80mv of hysteresis. an internal pull-up or pull-down resistor to change these values is available upon request. as a result, this pin must not be left floating, and should be tied to v in if not used. a 1k to 10k pull-up resistor is required for applications that use open collector or open drain outputs to control the enable pin. the enable pin may be connected directly to v in for applications with outputs that are always on. power-good operation pg is a logic output that indicates the status of v out , current limit tripping, and v in . the pg flag is an open-drain nmos that can sink up to 10ma during a fault condition. the pg pin requires an external pull-up resistor typically connected to the v out pin. the pg pin should not be pulled up to a voltage source greater than v in . pg goes low when the output voltage drops below 84% of the nominal output voltage, the current lim it faults, or the input voltage is too low. pg functions during shutdown, but not during thermal shutdown. for applications not using this feature, connect this pin to ground. soft-start operation the soft-start circuit controls the rate at which the output voltage rises up to regulation at power-up or ldo enable. this start-up ramp time can be set by adding an external capacitor from the ss pin to ground. an internal 2a current source charges up this c ss and the feedback reference voltage is clamped to the voltage across it. the start-up time is set by equation 3: equation 4 determines the c ss required for a specific start-up in-rush current, where v out is the output voltage, c out is the total capacitance on the output and i inrush is the desired in-rush current. the external capacitor is always discharged to ground at the beginning of start-up or enabling. external capacitor requirements external capacitors are required for proper operation. careful attention must be paid to the layout guidelines and selection of capacitor type and value to ensure optimal performance. output capacitor the isl80121-5 applies state-of-the -art internal compensation to keep the selection of the output capacitor simple for the customer. stable operation over full temperature, v in range, v out range and load extremes are guaranteed for all capacitor types and values assuming a minimum of 10f x5r/x7r is used for local bypass on v out . this output capacitor must be connected to the v out and gnd pins of the ldo with pcb traces no longer than 0.5cm. there is a growing trend to use very-low esr multilayer ceramic capacitors (mlcc) because they can support fast load transients and also bypass very high frequency noise from other sources. however, the effective capacitance of mlccs drops with applied voltage, age, and temperature. x7r and x5r dieletric ceramic capacitors are strongly recommended as they ty pically maintain a capacitance range within 20% of nominal voltag e over full operating ratings of temperature and voltage. additional capacitors of any value in ceramic, poscap, alum/tantalum electrolytic types may be placed in parallel to improve psrr at higher frequenc ies and/or load transient ac output voltage tolerances. input capacitor for proper operation, a minimu m capacitance of 10f x5r/x7r is required at the input. this ceramic input capacitor must be connected to the v in and gnd pins of the ldo with pcb traces no longer than 0.5cm. figure 11. increasing i limit (r set to gnd) 0.7 0.9 1.1 1.3 1.5 1.7 220200 r set (k ? ) current limit (a) i limit 0.75 2.9 2 v in 1 ? () r set k () ----------------------------------------------- ? = (eq. 2) figure 12. decreasing i set (r set to v in ) -0.05 0.05 0.15 0.25 0.35 0.45 0.55 0.65 0.75 40 400 r set (k ? ) current limit (a) t start c ss x0.5 () 2 a -------------------------- - = (eq. 3) c ss v out xc out x2 a () i inrush x0.5v ------------------------------------------------- - = (eq. 4)
isl80121-5 9 fn7713.5 june 22, 2012 power dissipation and thermals the junction temperature must not exceed the range specified in the ?recommended operating conditions (note 7)? on page 4. the power dissipation can be calculated by using equation 5: the maximum allowable ju nction temperature, t j(max) and the maximum expected ambi ent temperature, t a(max) determine the maximum allowable power dissipation, as shown in equation 6: ja is the junction-to-ambient thermal resistance. for safe operation, ensure that the power dissipation p d , calculated from equation 5, is less than the maximum allowable power dissipation p d (max) . the dfn package uses the copper ar ea on the pcb as a heat-sink. the epad of this package must be soldered to the copper plane (gnd plane). figure 13 shows a curve for the ja of the dfn package for different copper area sizes. thermal fault protection the power level and the thermal impedance of the package (+48c/w for dfn) determine when the junction temperature exceeds the thermal shutdown temperature. in the event that the die temperature exceeds around +160c, the output of the ldo will shut down until the die temperature cools down to about +130c. general power pad de sign considerations figure 14 shows the recommended use of vias on the thermal pad to remove heat from the ic. this typical array populates the thermal pad footprint with vias spaced three times the radius distance from the center of each via. small via size is advisable, but not to the extent that so lder reflow becomes difficult. all vias should be connected to the pad potential, with low thermal resistance for efficient heat tran sfer. complete connection of the plated through- hole to each plane is important. it is not recommended to use ?thermal relief ? patterns to connect the vias. p d v in v out ? () i out v in i gnd + = (eq. 5) p dmax () t jmax () t a ? () ja ? = (eq. 6) figure 13. 3mmx3mm 10 ld dfn on 4-layer pcb with thermal vias ja vs epad-mount copper land area on pcb 46 44 42 40 38 36 34 ja (c/w) 2 4 6 8 10 12 14 16 18 20 22 24 epad-mount copper land area on pcb, mm2 figure 14. pcb via pattern
isl80121-5 10 fn7713.5 june 22, 2012 revision history the revision history provided is for inform ational purposes only and is believed to be accurate, but not warranted. please go t o web to make sure you have the latest revision. date revision change 6/6/12 fn7713.5 1. changed pod l10.3x3 on page 12 to late st revision from 6 to 7. change pod is as follows: removed package outline and included center to center distance between lands on recommended land pattern. removed note 4 "dimension b applies to th e metalized terminal and is measured between 0.18mm and 0.30mm from the terminal tip." since it is not applicable to this package. renumbered notes accordingly. 5/29/12 1. ?input voltage requirements? on page 7 changed input voltages from ?2.2v? to ?5v? 5/23/12 1. page 1: on 3rd paragraphs firs t sentence ?cmos? changed to ?bicmos?. 2. page1: 1st paragraph sentence changed from: ?this ld o operates from input voltages of 2.2v to 6v. the isl80121-5 has a nominal output voltage of 5v?. t0: ?the isl80121-5 operates from input voltages of 5v to 6v with a nominal output voltage of 5v?. 3. page 2: removed note in ordering information: ?the 1 .5v, 3.3v and 5v fixed output voltages will be released in the future. please contact intersil marketing for more details?. 4. page 4: recommended operation conditions ?v in relative to gnd changed from 2.2v to 6v to 5v to 6v? 5. page 4: recommended operation conditions removed ?v out range line 800mv t0 5v? 9/19/11 fn7713.4 table 1 on page 1 updated to include more information on intersil's 1a ldo portfolio. 4/22/11 fn7713.3 in figure 8 on page 7, corrected label from ?v out (50v/div)." to ?v out (50mv/div)." in ?dc output voltage accuracy? on page 4, corrected the max value from -1.8 to +1.8. 2/1/11 fn7713.2 1. page 1, paragraph 2, ?the programmable current limiting improves system reliability of applications? changed to ?the programmable cu rrent limiting improves system reliability of end applications.? 2. page 1, features, ?programmable soft-starting? changed to ?programmable soft-start? 3. made subbing consistent throughout document. 4. page 3, epad description ?directly to gnd plane is opti onal.? changed to ?directly to gnd plane is required for thermal considerations. see ?power dissipatio n and thermals? on page 9 for more details.? 5. page 5, removed notes in electrical spec table, which read:?minimum capacitor of 10f x5r/x7r on v in and v out required for stability.? and ?if the current limit fo r in-rush current is acceptable in application, do not use this feature. used only when large bulk capacitance required on v out for application.? 6. page 5, electrical specifications, pg pin characteristics, v out pg flag threshold a.typical "85" changed to ?84? %v out 7. page 9, after thermal fault protection section a.added ?general power pad design co nsiderations? section with figure 14. 8. all pgood changed to pg throughout. 1/28/11 changed theta ja from 51c/w to 48c/w. 1/25/11 1.page 1, features a."200vrms output noise? change d to ?210 vrms output noise? 2.page 1, typical applications, right side figure a.resize "v out " (pin2) and ?sense? (pin3) 3.page 8, equation 4 a.extra parenthesis ")" removed 1/21/11 page 1 before features added table of key differences. page 2 block diagram - removed ?adj voltage version? and left the ?sense? connection. page 3 pin number 8, description, 2nd sentence: ?curre nt limit is 0.75ma...? changed to ?current limit is 0.75a?" page 4 electrical specifications, ac characteristics, input supply ripple rejection test conditions and typical values changed from ?f = 1khz, iload = 1a, f = 120hz, iload = 1a? to ?f = 1khz, iload = 1a, f = 1khz, iload = 100ma? page 6, figure 3 - x-axis label changed from ?output current (ma)" to ?output current (a) page 8, figure 12 - a.figure label change. ?in? in "v in " was subscripted. 12/6/10 fn7713.1 1. in ?block diagram? on page 2: a. added ?adj adjustable voltage version? pin. added ?fixed voltage version? to ?sense? pin 2. on page 4: ?ground pin current? test conditions a. replaced "v out +0.4v" with "2.2v" on both lines 12/2/10 fn7713.0 initial release.
isl80121-5 11 intersil products are manufactured, assembled and tested utilizing iso9000 quality systems as noted in the quality certifications found at www.intersil.com/design/quality intersil products are sold by description only. intersil corporat ion reserves the right to make changes in circuit design, soft ware and/or specifications at any time without notice. accordingly, the reader is cautioned to verify that data sheets are current before placing orders. information furnished by intersil is believed to be accurate and reliable. however, no responsi bility is assumed by intersil or its subsid iaries for its use; nor for any infringem ents of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of i ntersil or its subsidiaries. for information regarding intersil corporation and its products, see www.intersil.com fn7713.5 june 22, 2012 for additional products, see www.intersil.com/product_tree products intersil corporation is a leader in the design and manufacture of high-performance analog semico nductors. the company's product s address some of the industry's fastest growing markets, such as , flat panel displays, cell phones, handheld products, and noteb ooks. intersil's product families address power management and analog sign al processing functions. go to www.intersil.com/products for a complete list of intersil product families. for a complete listing of applications, rela ted documentation and related parts, please see the respective device information p age on intersil.com: isl80121-5 to report errors or suggestions for this data sheet, please go to: www.intersil.com/askourstaff fits are available from our web site at: http://rel.intersil.com/reports/search.php
isl80121-5 12 fn7713.5 june 22, 2012 package outline drawing l10.3x3 10 lead dual flat package (dfn) rev 7, 10/11 located within the zone indicated. the pin #1 identifier may be unless otherwise specified, tolerance : decimal 0.05 tiebar shown (if present) is a non-functional feature. the configuration of the pin #1 id entifier is optional, but must be dimensions in ( ) for reference only. dimensioning and tolerancing conform to amse y14.5m-1994. 5. either a mold or mark feature. 3. 4. 2. dimensions are in millimeters. 1. notes: bottom view detail "x" side view typical recommended land pattern top view (4x) 0.10 index area pin 1 pin #1 index area c seating plane base plane 0.08 see detail "x" c c 4 5 5 a b 0.10 c 1 1.00 0.20 8x 0.50 2.00 3.00 (10x 0.23) (8x 0.50) 2.00 1.60 (10 x 0.55) 3.00 0.05 0.20 ref 10 x 0.23 10x 0.35 1.60 max (4x) 0.10 ab c m 0.415 0.23 0.35 0.200 2 2.85 typ

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